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AUCSC350 - Computer Organization and Architecture II

Architecture of historical and contemporary computer systems, including CPU chips and buses, memory, secondary memory devices, and I/O interfaces. Performance enhancement techniques, including prefetching, pipelining, caching, branch prediction, out-of-order and speculative execution, explicit parallelism, and predication are discussed. The course also includes the data path and control logic at the microarchitecture level; error detection and correction; floating-point number representation and calculation; fast arithmetic circuits; instruction sets and formats; and an overview of alternative and parallel architectures, including RISC/CISC, SIMD/MIMD, shared memory and message passing architectures. Prerequisite: AUCSC 250.

Winter Term 2019

Lecture Sections

Winter Term 2019 - LEC 1B01 (95088)

MWF 11:00:00 - 12:00:00 (AU G 2 286)
Instructor: rosanna@ualberta.ca - Profile

Lab Sections

Winter Term 2019 - LAB 1H01 (95089)

M 15:15:00 - 16:45:00 (AU G 2 286)
Instructor: rosanna@ualberta.ca - Profile

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